Drain Induced Barrier Lowering Value Research Articles

Strong Immunity to Drain-Induced Barrier Lowering in ALD-Grown Preferentially Oriented Indium Gallium Oxide Transistors.

Drain-induced barrier lowering (DIBL) is one of the most critical obstacles degrading the reliability of integrated circuits based on miniaturized transistors. Here, the effect of a crystallographic structure change in InGaO [indium gallium oxide (IGO)] thin-films on the DIBL was investigated. Preferentially oriented IGO (po-IGO) thin-film transistors (TFTs) have outstanding device performances with a field-effect mobility of 81.9 ± 1.3 cm2/(V s), a threshold voltage (VTH) of 0.07 ± 0.03 V, a subthreshold swing of 127 ± 2.0 mV/dec, and a current modulation ratio of (2.9 ± 0.2) × 1011. They also exhibit highly reliable electrical characteristics with a negligible VTH shift of +0.09 (-0.14) V under +2 (-2) MV/cm and 60 °C for 3600 s. More importantly, they reveal strong immunity to the DIBL of 17.5 ± 1.2 mV/V, while random polycrystalline In2O3 (rp-In2O3) and IGO (rp-IGO) TFTs show DIBL values of 197 ± 5.3 and 46.4 ± 1.2 mV/V, respectively. This is quite interesting because the rp- and po-IGO thin-films have the same cation composition ratio (In/Ga = 8:2). Given that the lateral diffusion of oxygen vacancies from the source/drain junction to the channel region via grain boundaries can reduce the effective length (Leff) of the oxide channel, this improved immunity could be attributed to suppressed lateral diffusion by preferential growth. In practice, the po-IGO TFTs have a longer Leff than the rp-In2O3 and -IGO TFTs even with the same patterned length. The effect of the crystallographic-structure-dependent Leff variation on the DIBL was corroborated by technological computer-aided design simulation. This work suggests that the atomic-layer-deposited po-IGO thin-film can be a promising candidate for next-generation electronic devices composed of the miniaturized oxide transistors.

Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric

This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an increase in ferroelectric thickness leads to a negative DIBL value due to the ferroelectric charge. Additionally, there exists an inverse relationship between ferroelectric thickness and channel length to achieve a DIBL value of 0. This condition is satisfied only with the increase of the ferroelectric thickness as the channel radius and insulator thickness increase. The DIBLs increase with higher remanent polarization and lower coercive field, remaining constant when the ratio of remanent polarization and coercive field is maintained.

Cryogenic Temperature and Doping Analysis of Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs

This work analyzes the impact of doping concentration on the temperature-dependent subthreshold current and swing saturation due to direct source-to-drain tunneling (DSDT) in short-channel silicon nanosheet (SiNS) metal–oxide–semiconductor field-effect transistors (MOSFETs). Furthermore, their influence on the drain-induced barrier lowering (DIBL) effect is investigated. Special attention is paid to the importance of the Fermi level and the average tunneling energy, whose energetic positions and distance from each other in the band diagram has a significant role in the temperature-dependent saturation behavior of the subthreshold current and swing, as well as the value of DIBL. Furthermore, we model and present with device simulation the existence of two merging subthreshold swings ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit {S}_ {\text {sth}}$ </tex-math></inline-formula> ) and DIBL effects with increasing gate bias at cryogenic temperatures. The merging is achieved by the superposition of the DSDT and thermionic emission (TE) current, which originate from their own dominated and visibly separated gate-bias regions.

Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical model

The present work investigates key attributes of metal–ferroelectric–metal–insulator–semiconductor (MFMIS) cylindrical nanowire (NW) transistor through a physics-based analytical model. The proposed NW MFMIS negative capacitance model is developed by solving the baseline short channel NW model coupled with one-dimensional Landau’s equation while considering the radial dependency of electric field in the ferroelectric, a key feature for NW architecture. Contrary to the expected behaviour of a short channel MOSFET, the analytical framework successfully captures the unconventional effects such as an increase in the threshold voltage, lowering of subthreshold swing, and a negative value of drain-induced barrier lowering with gate length downscaling in MFMIS cylindrical NW devices. Also, the impact of ferroelectric thickness, spacer induced polarization charge density, remnant polarization and coercive field on the unconventional short channel effects have been examined. The influence of different ferroelectric materials (Al–HfO2, Gd–HfO2, Y–HfO2, and HZO) on the extent of internal amplification has also been investigated. The developed model provides new insights into the functioning and optimization of NW MFMIS architecture for facilitating hysteresis-free high internal voltage amplification with sub-60 mV/decade swing.

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

In this work, we investigate a promising technique for improving the performance of silicon-on-insulator (SOI) silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory cells with ground plane in buried oxide (GPB). The physical phenomena that potentially degrade the performance of NAND flash memory cells at lower gate length are controlled by selection of an appropriate NAND flash device architecture. The various attributes of SONOS memory cells with GPB are compared with conventional SOI SONOS memory devices. It is shown that at the scaled gate length of 25 nm, a flash memory cell with GPB limits the short channel effects and achieves ~ 103 times higher memory speed. The short channel performance is evaluated by considering subthreshold slope (SS) and drain-induced barrier lowering (DIBL) parameters, which show significant improvement in SS along with relatively lower DIBL values at lower gate lengths in SONOS cells with GPB. The results highlight that a ~ 1.3 times wider memory window and ~ 2.4 times higher retention can be obtained over a period of 10 years in a SONOS GPB device in comparison to the SOI SONOS memory device. The present work provides guidelines to design highly dense flash memory devices while achieving improved reliability without altering the gate stack.

Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications

In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 $\times$ 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 $\times 10^{-5}$ A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.

Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors

This study proposes a new hybrid N channel/P substrate for junctionless field-effect transistors (JL-FET) by using electron beam lithography adjustment for the shell structure. The nanowire (NW) shell JL-FET exhibits the superior electrical properties, including high ON/OFF current ratio of 6 × 106, low subthreshold swing (SS) of 95 mV/decade and drain-induced barrier lowering value (DIBL) of 50 mV/V. This NW shell structure JL-FET is simple to fabricate, and highly favorable for use in advanced System-on-panel (SoP) and three-dimensional (3-D) stacked IC applications.

Analysis of a high-performance ultra-thin body ultra-thin box silicon-on-insulator MOSFET with the lateral dual-gates: featuring the suppression of the DIBL

An inspiring UTBB SOI MOSFET structure with enhanced immunity to the drain-induced barrier lowering (DIBL) is analyzed. The structure includes the dual-gates in the lateral direction. The voltage difference is applied between the dual-gates, through which the electrostatic potential and the energy band along the channel are modified and the electrical performance is boosted. The electrical characteristics are investigated by measuring the electron concentration, the conduction band energy level, and the potential at the front-surface. The impact of the negative voltage bias applied to the right gate on the performance of the new device is studied, and compared to that of the conventional ultra-thin body ultra-thin box silicon-on-insulator (UTBB SOI) devices. The results reveal that the undesirable DIBL values are lower in this innovative device than that in the conventional UTBB SOI MOSFET.

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

We investigate the performance of hysteresis-free short-channel negative-capacitance FETs (NCFETs) by combining quantum-mechanical calculations with the Landau–Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of drain-induced barrier lowering is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance in the output characteristics of the NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresis-free NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.

Enhancement mode AlGaN/GaN double heterostructure high electron mobility transistor with F plasma treatment

Effects of double heterostructure materials (AlGaN/GaN/AlGaN/GaN) with different GaN channel thickness values (14 nm, 28 nm, 60 nm) on the high electron mobility transistor (HEMT) are simulated by using silvaco, and furthermore, the differences in characteristic among the enhancement mode devices made from such double heterostructure materials with different F injection doses (150 W, 135 W) are also simulated. The simulation results show that the threshold voltage shifts towards positive direction and the saturation current decreases as the GaN channel thickness decreases. The two-dimensional electron gas (2 DEG) density could be reduced as GaN channel thickness decreases due to piezoelectric polarization weakened by backing AlGaN barrier. Combining F plasma treatment and double heterostructure material, the enhancement mode device with high positive threshold voltage is successfully developed. The DC characteristics of the enhancement mode devices with different GaN channel thickness values are analyzed comparatively, and the simulation results are validated by using the experimental results. The threshold voltages of these enhancement mode devices with GaN channel thickness values of 14 nm, 28 nm, and 60 nm reach 1.1 V, 0.8 V, and 0.3 V, respectively. The maximum transconductance values of these enhancement mode devices with GaN channel thickness values of 14 nm, 28 nm, and 60 nm reach 115 mS/mm, 137 mS/mm, and 198 mS/mm, respectively. The thinner GaN channel thickness in the double heterostructure could reduce the depth of quantum well and 2 DEG density, so that the device with a GaN channel thickness of 14 cm has a lower saturation current. The breakdown voltages and gate reverse leakage currents of the three kinds of devices are investigated, and the device with a thinner GaN channel has a lower leakage current and higher breakdown voltage due to weakened vertical electrical field in thinner channel double heterostructure. The damage of channel mobility in F plasma treatment is weakened by using a lower plasma power (135 W), and the enhancement mode device without annealing process demonstrates a better saturation current and transconductance characteristic. The results of the device with annealing confirm that the plasma damage is depressed at an F injection power of 135 W. The threshold voltage temperature stability of 14 nm GaN channel thickness device is studied, and Vth is only 0.4 V after 350 ℃ 2 min annealing process. Drain induced barrier lowering (DIBL) effects of the HEMTs with double heterostructures are investigated, and the DIBL value of the14 nm GaN channel device is 16 mV/V. The DIBL value indicates a good limiting property of the 2 DEG in double heterostructure device.

Carbon doped GaN buffer layer using propane for high electron mobility transistor applications: Growth and device results

The creation of a semi insulating (SI) buffer layer in AlGaN/GaN High Electron Mobility Transistor (HEMT) devices is crucial for preventing a current path beneath the two-dimensional electron gas (2DEG). In this investigation, we evaluate the use of a gaseous carbon gas precursor, propane, for creating a SI GaN buffer layer in a HEMT structure. The carbon doped profile, using propane gas, is a two stepped profile with a high carbon doping (1.5 × 1018 cm−3) epitaxial layer closest to the substrate and a lower doped layer (3 × 1016 cm−3) closest to the 2DEG channel. Secondary Ion Mass Spectrometry measurement shows a uniform incorporation versus depth, and no memory effect from carbon doping can be seen. The high carbon doping (1.5 × 1018 cm−3) does not influence the surface morphology, and a roughness root-mean-square value of 0.43 nm is obtained from Atomic Force Microscopy. High resolution X-ray diffraction measurements show very sharp peaks and no structural degradation can be seen related to the heavy carbon doped layer. HEMTs are fabricated and show an extremely low drain induced barrier lowering value of 0.1 mV/V, demonstrating an excellent buffer isolation. The carbon doped GaN buffer layer using propane gas is compared to samples using carbon from the trimethylgallium molecule, showing equally low leakage currents, demonstrating the capability of growing highly resistive buffer layers using a gaseous carbon source.

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering

The optimum device for a standby power reduction scheme utilizing drain-induced barrier lowering (DIBL) has been investigated. In this circuit scheme, the supply voltage is lowered in the standby mode to relax the DIBL effect, resulting in the increase in threshold voltage and the reduction of subthreshold leakage current. It is found that a critical supply voltage, Vo, exists that determines the optimum DIBL value for the standby power suppression. When the supply voltage can be lowered less than Vo in the standby mode, a device with a larger DIBL value is preferable to a device with a smaller DIBL value in terms of the standby power reduction. It is also shown that the fluctuations of standby power due to the threshold voltage variation can be suppressed in this circuit scheme utilizing DIBL.